1. Technical Field
This invention relates to electronic systems, and more particularly to a method and apparatus for converting between a multi-bit time division multiplexed bus and a single-bit time division multiplexed bus.
2. Background Information
Modern electronic systems frequently make use of a backplane (sometimes called a "motherboard") having connectors for multiple plug-in cards (sometimes called "daughterboards"). In FIG. 1 is a block diagram of a backplane based electronic system. Such a system may be used for a computer architecture, a communications processing system, and a wide variety of other electronic systems.
As shown in FIG. 1, a backplane 10 is coupled by a low speed time-division multiplexed (TDM) multiple bit (i.e., parallel or Multi-Bit TDM) bus 12 to several low speed cards 14 and to a high speed card 16. The Multi-Bit TDM bus 12, the backplane 10, and the low speed cards 14 typically operate at a clock rate of about 20 MHz or less (this rate is exemplary only).
The high speed card 16 contains high speed components 18 that may operate, for example, at an internal clock rate in excess of 100 MHz (this rate is exemplary only). Such a rate may be needed, for example, in certain signal processing applications where incoming and outgoing data are inherently serial, such as in digital telephony. A high speed time-division multiplexed single-bit (i.e., serial or Single-Bit TDM) bus 20 is used for internal data communications.
Using a lower speed Multi-Bit TDM bus 12 on the backplane 10 rather then a high speed Single-Bit TDM bus 20 throughout the system allows use of slower, less expensive technology components for the backplane 10 and eliminates a requirement that all cards coupled to the backplane 10 be high speed. Consequently, signals passing between the Multi-Bit TDM bus 12 and the Single-Bit TDM bus 20 must be format converted (serial/parallel) and synchronized by means of a converter interface 22. Conventional designs use a phase lock loop to synchronize the high speed Single-Bit TDM bus 20 with the slower speed Multi-Bit TDM Bus 12.
The inventor has determined that it would be desirable to use a purely digital technique to perform such synchronization. The present invention provides such a technique.